For many years, computers are implemented with a processor (e.g. central processing unit “CPU”), semiconductor-based host memory, and one or more storage devices. Typically, the host memory is adapted to store data, such as instructions or other types of digital data for example, which needs to be quickly accessed by the processor. For instance, when the computer is in normal operation, the host memory usually contains main portions of its operating system and some or all of the application programs and related data that are currently being used. One type of host memory is random access memory (RAM) that is located in close physical proximity to the processor of the computer.
In contrast with host memory, a storage device provides a physical medium for storing larger amounts of data that is less frequently used than the data contained in host memory. Hence, in order to reduce overall computer costs, the size of host memory is typically limited, which requires data to be frequently transmitted from host memory to the storage device.
During each transmission to the storage device, a time delay is normally experienced. This time delay is the sum of both memory access latency and the data transmit time over a transmit path. The data transmit time is based on the link rate being the rate of communication to the storage device over an interconnect.
When the memory access latency is greater than the data transmit time for a given link rate, the storage device needs to prefetch data frames in order to eliminate link idle time on the transmit path.
Currently, this prefetch rate is a constant value that is either hardcoded or programmed into a control register by driver software of the storage device. The prefetch rate is chosen based on a number of factors, such as estimated average memory access latency and a data transmit time that is fixed based on the estimated transmission rate of the selected interconnect. The maximum number of data frames to prefetch is based on available transmit buffer space.
However, in actual operating conditions, the memory access latency is not a constant value, but varies in response to operational conditions of the computer. These operational conditions may involve increased or decreased memory traffic within the computer or alterations in the type of interface or communication protocols utilized by the storage device. In short, the current prefetch mechanism does not account for real-time operational conditions detected during various prefetch cycles.